Observation of a I2C 8 bits write operation
I performed this test for 100kHz and 400kHz bus speed. However the result were the same.
Screenshot Labnation Smartscope A11 softwareversion 0.15.01 (2019-07-18)
Master is the transmitter and the slave device is the receiver.
Today (2019-07-20) I did a lot of new experiments with the TXT and one simple I2C 5V device. I am using a standard I2C level shifter between the TXT 3.3V and the device.
I tried a lot but the TXT was most of the time operating in 400Khz mode, even though the RoboPro elemnt was set to 100kHz I2C bus speed.
only on some moemnts after restarting the TXT there was a moment that the bus was in 100kHz speed; but this was only for a small moment and I was not able to reproduce it.
I notice also a funy behavior in the SDA:
This behavior fits into the description of the ACK-NACK ( chapter 3.1.6). The change in lower level, after the eight SCL puls is the moment that the receiver keep the SDA line low to confirm the ACK.
THe small puls is the moment that the receiver free the SDA. The spike in the SDA is only during the SCL low and does not matter, this is the moment that the master keep the SDA low to start the STOP-condition (( chapter 3..1.4).
The time between the end of the RoboPro element writeI2C (1 byte address and 1 byte of data) and the RoboPro element (readI2C) (i byte address and 1 byte of data) is betweem the +/- 150 to +/- 400 ms.